This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to complementary metal-oxide-semiconductor (CMOS) integrated circuits having metal-gate transistors with high dielectric constant gate dielectrics.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. As is fundamental in the art, reduction in the size of physical feature sizes of structures realizing transistors and other solid-state devices enables greater integration of more circuit functions per unit “chip” area, or conversely, smaller chip area consumed for a given circuit function. The capability of integrated circuits for a given cost has greatly increased as a result of this miniaturization trend.
Advances in semiconductor technology in recent years have enabled the shrinking of device minimum device feature size (e.g., the width of the gate electrode of a metal-oxide-semiconductor (MOS) transistor, which defines the transistor channel length) into the extreme sub-micron range. State of the art transistor channel lengths are now approaching the sub-20 nanometer regime. For MOS transistors, the scaling of transistor feature sizes into the deep submicron realm necessitates the thinning of the MOS gate dielectric layer. Conventional gate dielectric layers (e.g., silicon dioxide) have thus become extremely thin, which can be problematic from the standpoint of gate current leakage, manufacturing yield and reliability. In response to this limitation of conventional gate dielectric material, so-called “high-k” gate dielectrics, such as hafnium oxide (HfO2), have become popular. These dielectrics have higher dielectric constants than silicon dioxide and silicon nitride, permitting those films to be physically thicker than corresponding silicon dioxide films while remaining suitable for use in high performance MOS transistors. Because these high-k films are currently of lesser quality (from a defect density standpoint) than conventional dielectric material, typical conventional high-k gate dielectrics include both the high-k material and a high quality interface layer of silicon dioxide or the like; the silicon dioxide provides good dielectric integrity and quality, while the high-k material has a sufficiently high dielectric constant to make up for any degradation in electrical performance due to the interface layer.
As also known in the art, gate electrodes of metals and metal compounds, such as titanium nitride, tantalum-silicon-nitride, tantalum carbide, and the like are now also popular in modern MOS technology, especially in combination with high-k gate dielectrics. These metal gate electrodes eliminate the undesired polysilicon depletion effect, which is particularly noticeable at the extremely small feature sizes required of these technologies.
As fundamental in the art, attainment of the desired MOS transistor performance, specifically its threshold voltage, requires tuning of the characteristics of the gate material along with the dopant concentration and other physical parameters of the silicon channel region and source/drain regions. An important parameter in this tuning is the work function of the gate electrode. CMOS integrated circuits complicate this engineering, because the desired gate material work function is necessarily different for n-channel MOS transistors than for p-channel MOS transistors. For polysilicon gate material, this different work function is relatively easy to attain by way of ion implant, for example by exposing each gate electrode to the source/drain implants for its transistor; fine tuning is accomplished by threshold adjust implant to the channel region prior to gate formation.
While post-formation doping of metal gate electrodes has been used to adjust the metal gate work function, conventional high-k metal gate CMOS manufacturing processes often use different gate materials for n-channel and p-channel transistors. The provision of these different gate materials has resulted in structural issues in conventional CMOS integrated circuits, as will now be described in connection with FIGS. 1a through 1h. 
FIG. 1a illustrates, in cross-section, a portion of a high-k metal gate CMOS integrated circuit, partially fabricated according to a conventional process. The structure of FIG. 1a includes many features common to conventional polysilicon-gate CMOS integrated circuits, including p-well 4p and n-well 4n formed at the surface of a single-crystal silicon substrate. Isolation dielectric structure 5, for example in the form of a shallow trench isolation (STI) structure, is formed at the surface of the substrate, at the boundary between wells 4p, 4n; other instances of isolation dielectric structure 5 will be present in the integrated circuit to isolate separate transistors from one another, including within wells 4p, 4n, as known in the art. In the example of FIG. 1a, polysilicon gate structures 8 are disposed over selected locations of wells 4p, 4n, namely at the locations at which the eventual transistor gates will be formed, and overlying gate dielectric layer 7. N+ source/drain regions 6n are heavily-doped regions formed into p-well 4p on opposing sides of gate structures 8, and p+ source/drain regions 6p are similarly heavily-doped regions formed into n-well 4n on opposing sides of gate structures 8. Source/drain regions 6n, 6p are formed by conventional ion implantation in a self-aligned manner relative to gate structures 8, and to sidewall dielectric spacers 9 in place along the sides of gate structures 8. In this conventional process, spacers 9 are formed on opposing sides of gate structures 8 to define the eventual gate width of the metal-gate transistor. These spacers 9 themselves, or in combination with additional sidewall spacers, may be used to define lightly-doped-drain source/drain extensions, as known in the art.
In this conventional high-k metal gate technology, gate structure 8 and gate dielectric 7 are “dummy” structures, in that these elements do not become part of the finished integrated circuit. Rather, dummy gate structure 8 and dummy gate dielectric 7 serve as placeholders for defining the placement of source/drain regions 6n, 6p, and will be removed. In FIG. 1b, gap fill dielectric material 11 has been formed by chemical vapor deposition (CVD) overall, followed by chemical-mechanical polishing (CMP) to planarize the structure. Gap fill dielectric 11 fills in the spaces between dummy gate structures 8, and will generally remain throughout the formation of the high-k metal gate transistors. Subsequent etches remove dummy gate structures 8 and dummy gate dielectric 7, resulting in the structure of FIG. 1c. 
Referring to FIG. 1d, following the removal of dummy gate structures 8 and dummy gate dielectric 7, this conventional process deposits high-k dielectric 14 (typically overlying a thin interface layer, not shown in FIG. 1d). High-k dielectric 14 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) of a material with a relatively high dielectric constant as compared with silicon dioxide or silicon nitride; a typical conventional high-k dielectric material is HfO2, with other choices for high-k dielectric 14 also known in the art. Metal gate layer 15p is a layer of a metal or conductive metal compound that by its composition or by doping has a work function suitable for serving as the gate for p-channel MOS transistors with the desired threshold voltage for purposes of this integrated circuit. Examples of metal gate layer 15p include one or more of palladium, nickel, iridium, ruthenium, tungsten, molybdenum, tungsten nitride, carbonitrides including titanium carbonitride and tantalum carbonitride, oxynitrides, ruthenium oxide, TiAlN, TaCNO, and the like. Typically, a barrier metal layer (not shown) underlies the eventual metal gate layer 15p, to prevent interdiffusion among the materials. In this conventional process, metal gate layer 15p is then deposited overall, including over both n-well 4n at which a p-channel transistor will be formed and over p-well 4p at which an n-channel transistor will be formed.
Formation of the n-channel transistor is then performed, in this conventional process, by the dispensing and photolithographic patterning of photoresist 17, as shown in FIG. 1e, to protect the locations of the integrated circuit at which p-channel transistors are to be formed (i.e., n-well 4n) and expose those locations at which n-channel transistors are to be formed. An etch of metal gate layer 15p from those exposed locations results in the structure of FIG. 1e, with high-k gate layer 14 and any underlying interface layer remaining in place. Photoresist 17 remaining over n-well 4n is then removed.
Metal gate layer 15n, composed of a metal or conductive metal compound that by its composition or by doping has a work function suitable for serving as the gate for n-channel MOS transistors with the desired threshold voltage, is then deposited over both p-well 4p at which an n-channel transistor will be formed, and also over metal gate layer 14p remaining in place over n-well 4n. The material of metal gate layer 15n may consist of one or more elemental metals, ternary metals, metal alloys, and conductive metal compounds. Examples of metal gate layer 15n include tantalum, titanium, hafnium, and their nitride and carbide compounds; silicon nitride, aluminum nitride, and aluminum silicon nitride compounds; and combinations thereof. Typically, a barrier metal layer (not shown) underlies the eventual metal gate layer 15n, to prevent interdiffusion among the materials.
Following deposition of metal gate layer 15n, another barrier layer (not shown) is typically formed, followed by deposition of fill metal 18 overall. Fill metal 18 is intended to fill the remaining interior gap within the eventual gate electrodes of the two transistors. Examples of the conventional composition of fill metal 18 include tungsten, aluminum, and the like. The resulting structure is shown in an idealized representation in FIG. 1g. This structure is then subjected to CMP to remove the excess metal, such CMP typically continuing until the surface of gap fill dielectric material 11 is cleared.
It has been observed, according to this invention, that this conventional process necessarily involves the filling of a very narrow gap within the p-channel transistor gate structure, with fill metal 18. FIG. 1h, which is an inset of FIG. 1 g prior to the deposition of fill metal 18, illustrates this difficulty in additional detail. FIG. 1h shows the large number of layers that fill the space remaining after removal of dummy gate electrode 8 and dummy gate dielectric 7, according to a conventional process. Interface layer 12 is disposed at the bottom of the gate opening, on which high-k gate dielectric 14 is then formed. Barrier metal 16p is in contact with high-k gate dielectric 14, upon which metal gate layer 15p (for this p-channel MOS transistor) is then formed. Second barrier metal 16n is deposited over metal gate layer 15p, followed by metal gate layer 15n. Third barrier metal 17b is then formed over metal gate layer 15n, prior to the deposition of fill metal 18. As a result of this construction, gap 19 within the p-channel gate structure can be quite narrow, and thus difficult to fill with fill metal 18. This gap 19 has been observed to be sufficiently narrow as to cause problems in step coverage of fill metal 18 (i.e., thinning or opens at the corners of barrier metal layer 17b), as well as voids within the gate structure itself. Such voids can result in increased resistivity in conduction along the gate electrode, and thus non-uniform potential along the gate electrode for individual transistors, and inconsistencies in operation among a population of transistors.
In addition, the formation of metal gate layers 15n, 15p adjacent to one another in the same gate structure raises the risk of interdiffusion of material between the two metals, particularly from the overlying metal gate layer 15n into the underlying metal gate layer 15p. Such interdiffusion can change the work function of the intended gate metal (metal gate layer 15p in the example of FIG. 1h), and thus degrade the intended transistor performance. Accordingly, barrier metal layer 16n is necessary between these two metal gate layers, which inserts another layer of metal into the narrowing gap as well as complicating the overall manufacturing process.
By way of further background, commonly owned U.S. Pat. No. 8,062,966, issued Nov. 22, 2011, entitled “Method for Integration of Replacement Gate in CMOS Flow”, and incorporated herein by this reference, describes a high-k metal gate structure and process, according to which CMOS integrated circuits are constructed using a replacement gate process.